The following paper discusses the modelling and analysis of the real-time properties of superscalar processor architectures at the University of Newcastle-upon-Tyne, UK. It discusses how CP-nets can be used to model and investigate different aspects of modern processor architectures, such as parallel execution of instructions, branch prediction, and the use of instruction caches. The paper concludes that it is relatively easy and straightforward to capture most of the processor architecture concepts considered by means of the CPN modelling language. The constructed models were investigated by means of simulation, where the timing of the executed instructions was displayed graphically by means of a simple Tcl/Tk program providing a post-processing of the output from the Design/CPN simulator.
This paper describes how CP-nets and the CPN tools were used to specify and analyse the behavioural aspects of a VLSI chip used in a new super computer. The modelling and analysis of the hardware design were done at the register transfer level. The project was carried out at Meta Software, Cambridge MA in cooperation with a manufacturer of supercomputers.
The project is also described in Chapter 10 of:
The following paper describes how CP-nets and the CPN tools were used to model a cascade of arbiters. The main motivation for the work is the observation that CPN models perfectly meet circuit designers' need to visualise and experiment during the development of their designs. Moreover, designers can use state space to validate the correctness of the design.
The project is also described in Chapter 11 of:
