# Comments are nice
# Here a macro definition specifying the source files
SRC	=	modula.cpp modulb.cpp main.cpp
# another macro, as SRC, but replace .cpp by .o
OBJ	=	$(SRC:.cpp=.o)
CC	=	g++
CFLAGS	=	-Wall -O -g

# Here is the rule of how to get from a .cpp file to a .o file:
# The $< macro expands into a source file name
.cpp.o:
	$(CC) $(CFLAGS) -c $<

# a dependency: to make the target "all", first do the target "pgm"
all:	pgm

# another dependency: to make the target pgm, make the files that OBJ
# expands to, here "modula.o modulb.o main.o", then link the object
# files with the $(CC) command into the executable pgm
pgm:	$(OBJ)
	$(CC) $(OBJ) -o pgm

# How does make find out how the $(OBJ) object files are made? It has
# default rules for this, eg. the .cpp.o rule above.